1. Field of the Invention
The invention relates to an output stabilization circuit and CML circuit using the same, and more particularly to an output level stabilization technique for suppressing variations in output level of a CML circuit caused by noises.
2. Related Art
In recent years, the operating frequency of LSI has been raised; and in the high-speed signal transmission in LSI, analog signals have been increasingly used. Particularly, there have been used numerous analog high-speed transmission systems using circuits based on CML (Current Mode Logic). CML circuits have been disclosed, for example, in Japanese Utility Model Laid-Open No. 2-73827 (Patent Document 1) and Japanese Patent Laid-Open No. 7-307658 (Patent Document 2). FIG. 3 illustrates an exemplary typical CML circuit 1.
Referring to FIG. 3, a pair of complementary input signals IN and INB are supplied to gates of differential-pair MOS transistors T1 and T2 having sources connected to each other; and a pair of complementary output signals OUT and OUTB are outputted from drains of these transistors T1 and T2. Resistors R1 and R2 are drain resistors of the transistors T1 and T2, respectively. A MOS transistor T3 acting as the current source is connected between the source connection point of the transistors T1 and T2 and a reference voltage point (in this example, ground); and reference voltage Vcs is supplied to a gate of this transistor T3.
The operation of the above CML circuit has been disclosed in Patent Documents 1 and 2, so this is generally known. Hence, an explanation thereof is omitted.
The above CML circuit 1 has a problem that, when noises are added to reference voltage Vcs, the output level becomes unstable, causing increased jitter and thus lowering the quality of signal transmission. Accordingly, when a CML circuit is used, tolerance to noise is required. In order to satisfy this requirement, there has been proposed a circuit illustrated in FIG. 4. FIG. 4 illustrates an exemplary circuit having a reference voltage generation circuit 2 for generating reference voltage Vcs of the CML circuit 1.
Referring to FIG. 4, the reference voltage generation circuit 2 has a replica circuit including MOS transistors T4 and T5 and a resistor R3. This replica circuit has the same circuit constant as the CML circuit 1, and has the same configuration as the one-side of the differential pair of the CML circuit 1. More specifically, the replica circuit is constituted of the transistor T4 having the same characteristics as the current source transistor T3 of the CML circuit 1, the transistor T5 having the same characteristics as the transistor T1 being one of the differential-pair transistors of the CML circuit 1, and the resistor R3 having the same resistance value as the drain resistor R1 of the transistor T1 of the CML circuit 1. The gate input of the transistor T5 is fixed at a high level.
Reference voltage Vcs is applied to the gate of the transistor T4; this reference voltage is generated by an analog comparator 21. Drain output Vrep of the transistor T5 of the replica circuit is applied via a feedback resistor R4 to a positive-phase input of this comparator 21. Voltage division output Vref obtained through voltage division between voltage divider resistors R5 and R6 is applied to a negative-phase input of the comparator 21.
This voltage division output Vref is set identical to the low level output voltage of the CML circuit 1; thus, the resistors R5 and R6 are set to have a resistance value ratio therebetween so that the voltage division output Vref is identical to the low level output voltage of the CML circuit 1. Drain voltage Vrep of the transistor T5 being the output of the replica circuit is identical to the output voltage of the CML circuit 1 when the input (IN or INB) of the CML circuit 1 has a high level.
The operation of the circuit of FIG. 4 will be described below. First, the operation in a low frequency range will be described. When output Vrep of the replica circuit is higher than voltage division output Vref obtained through the resistors R5 and R6, output Vcs of the analog comparator 21 rises and thus output Vrep of the replica circuit lowers. Conversely, when output Vrep of the replica circuit is lower than voltage division output Vref, output Vcs of the analog comparator 21 lowers and thus output Vrep of the replica circuit rises. This operation causes output Vrep of the replica circuit to converge at the time of reaching voltage division output Vref, so that output Vrep of the replica circuit becomes identical to the low level output voltage (Vref) of the CML circuit.
Here, when an open-loop gain between the comparator 21 and replica circuit is Go, a closed-loop gain Gc of a feedback circuit from the replica circuit to the comparator 21 is expressed as Gc=Go/(1+Go). Thus, the gain of the comparator 21 is raised to maximize Go, so that Gc is made closest to “1”, whereby the difference between output Vrep of the CML circuit 1 and voltage division output Vref obtained through the resistors R5 and R6 can be reduced, allowing stabilizing output Vrep.
The operation in which high-frequency noise is taken into consideration will be described. When an external high-frequency noise inputs, and when the above described closed-loop high-frequency gain of the feedback circuit exceeds “1”, the high-frequency noise is amplified. As described above, the gain of the comparator 21 has been raised in view of the low-frequency operation, so the gain of the comparator 21 cannot be lowered. Thus, a resistor R4 is inserted in the feedback circuit section, so that only the gain of the whole closed loop is lowered.
In this way, when the resistor R4 is inserted in the feedback circuit, the closed-loop gain can be lowered to suppress the noise amplification. However, the phase of high-frequency noise varies depending on the resistance value, and resonance may occur according to the amplitude of this variation. This indicates that there exists a particular frequency which corresponds to a given resistance value and constitutes a weak point regarding noise amplification. Effects caused by such a frequency must be eliminated.